Himax Technologies launched the HE Series indirect Time-of-Flight (iToF) Depth Decoder ICs on June 30, targeting robotics, industrial automation, and AI vision applications. The chips use a hardware-based depth processing pipeline that Himax says delivers lower latency than software-based approaches running on a host processor.
The IC accepts RAW data input at resolutions up to 640×480 and frame rates up to 240 fps, in both single-frequency and dual-frequency operating modes. After decoding, it simultaneously outputs 2D grayscale images and 3D depth data through MIPI and USB interfaces at up to 120 fps. Himax has validated the chip for compatibility with existing VGA-resolution iToF sensors, reducing the redesign burden when engineers swap in a new decoder.
What's new here is where the processing happens: moving depth computation from host software to dedicated silicon reduces CPU headroom requirements on the host side, which allows designers to use lower-power compute boards in the overall system.
The IC includes depth noise reduction, flying pixel removal, and temporal filtering to maintain accuracy in high-speed motion and complex environments. Himax ships an SDK and an iToF Calibration Library covering Fixed Pixel Phase Noise (FPPN) correction, Wiggling Compensation, Thermal Compensation, camera intrinsic calibration, and lens distortion correction.
The HE Series ships in two variants. The HE-1 handles depth decoding. The HE-2 adds an integrated RGB ISP, an MJPEG encoder, and an RGB-D alignment engine that fuses color and depth data at the IC level, reducing host-side processing load. The HE-2 also carries an on-chip Neural Processing Unit for eye tracking, gesture recognition, and other AI inference workloads.
Optical module maker OFILM has already incorporated the HE Series into its RoboVision module, which targets object picking, obstacle avoidance, environment mapping, and autonomous navigation. The early design-in by a volume optical module manufacturer suggests the integration path is established, which typically shortens qualification timelines for other system builders evaluating the same sensor-decoder pairing.
